1. Field of the Invention
The present invention relates to semiconductor devices and their manufacturing methods, and more particularly, to a structure of a semiconductor device permitting relaxation of stress after mounting and a manufacturing method of the same.
2. Description of the Background Art
In recent years, there exist increasing demands for more compact and lightweight electronic components such as mobile telephones and mobile information equipment, and accordingly, miniaturization and more dense integration of semiconductor devices have been rapidly advancing. To this end, several proposals have been made. One proposal is bare chip mounting in which a large scale integrated (LSI) circuit chip is mounted directly on a circuit board. Another proposal is to provide a semiconductor device with a so called chip size package (CSP) structure in which the shape of the semiconductor device is made to follow that of the LSI chip as close as possible for miniaturization. In the semiconductor device with this CSP structure, peripheral type electrode arrangement that is common to ordinary LSI chips is converted, by a rewiring step, to area array type electrode arrangement that is advantageous for increasing the number of pins.
FIGS. 1A-1C show an example of the semiconductor device that is used in conventional bare chip mounting. As shown in FIG. 1A, the semiconductor device 21 is formed of a bare chip 22 and a plurality of connecting portions 24. As shown in FIG. 1B, bare chip 22 is connected via connecting portions 24 to electrodes 25a on a printed circuit board 25. With this structure, however, large thermal stress is generated due to a difference of thermal expansion of bare chip 22 and printed circuit board 25, and it is known that connecting portion 24 is unreliable.
Thus, as shown in FIG. 1C, spacing 27 between the undersurface of bare chip 22 and the surface of printed circuit board 25 is generally filled with resin 26 (this is called xe2x80x9cunderfillxe2x80x9d) to relax the thermal stress occurring in connecting portions 24. Such underfill of spacing 27 between the undersurface of bare chip 22 and the surface of printed circuit board 25, however, makes repair of bare chip 22 extremely difficult. Thus, although the structure of the semiconductor device shown in FIGS. 1A-1C may enable ultimate miniaturization and extremely dense mounting, it has failed to spread due to various reasons as follows: an increase of cost because additional steps are required for implanting and curing resin 26; a low degree of freedom because repair of bare chip 22 is essentially impossible; and difficulty in handling of bare chip 22 itself. Therefore, there has been a demand for a semiconductor device which permits high-density mounting as in the bare chip mounting, which can be implemented at the least possible cost, and which ensures reliability not only in a single package, but also after mounting.
Several inventions have been disclosed to meet such demands. For example, an invention disclosed in Japanese Patent Laying-Open No. 6-177134, as shown in FIG. 2, is directed to a bump structure of an electronic component. This includes a terminal electrode 32 on an IC chip 31, an insulating layer 33, barrier metal layers 34, 35 and 36 covering terminal electrode 32, a solder bump 37, a coating layer 38, and a resin layer 41 formed between terminal electrode 32 and barrier metal layer 34. This resin layer 41 formed between terminal electrode 32 and barrier metal layer 34 acts to relax thermal stress, thereby improving reliability.
An invention disclosed in Japanese Patent Laying-Open No. 10-12619 or 10-79362, as shown in FIGS. 3A and 3B, is directed to a semiconductor device which includes a substrate 56, a bump 52 arranged on substrate 56, a resin layer 53 sealing bump 52, and an externally connecting bump 50 formed at a tip of bump 52 that is exposed from resin layer 53. Bump 52 is sealed by resin layer 53, and thus, stress produced at a junction of an electrode on substrate 56 and externally connecting bump 50 is relaxed to improve reliability.
An invention disclosed in Japanese Patent Laying-Open No. 8-102466, as shown in FIGS. 4A-4C, includes a wafer 60, a passivation film 62 covering wafer 60, an electrode pad 61 formed on wafer 60, an aluminum interconnect 64 formed to connect to electrode pad 61 and extend within the semiconductor chip region, a nickel plate 65 formed on aluminum interconnect 64, a cover coat film 66 covering the entire surface of wafer 60, and a solder bump 68 formed in an aperture exposing the surface of nickel plate 65.
An invention disclosed in Japanese Patent No. 2924923, as shown in FIG. 5, includes: a semiconductor chip 70; a flexible lead 73 connecting an on-chip electrode pad 71 and an external electrode 72; a flexible sheet insert 74 posed between external electrode 72 and the chip 70; a hole 76 opened in sheet insert 74 corresponding to on-chip electrode 72; and a sealer 75 to fill in hole 76. Stress occurring after mounting the semiconductor device on a printed circuit board 77 via external electrode 72, due to difference of thermal expansion between the board 72 and the chip 70, is relaxed taking advantage of the flexibility of sheet insert 74, lead 73 and sealer 75, thereby improving reliability.
Although the conventional techniques illustrated in FIGS. 2-5 have been proposed to improve reliability by minimizing thermal stress created in the connecting portion and to improve handling as compared to the case of the flip chip bonding of bare chips, they exhibit the following problems.
Assume that thermal stress is produced after mounting the semiconductor device according to the invention disclosed in Japanese Patent Laying-Open No. 6-177134. In this case, as shown in FIG. 6, strain will be accumulated in solder bump 37 on its semiconductor chip side, which may cause a crack 42 to be created, leading to fracture.
Assume again that thermal stress is produced after mounting the semiconductor device of the invention disclosed in Japanese Patent Laying-Open No. 10-12619 or 10-79362. Then, strain will again accumulate in bump 52 in its root portion, as shown in FIG. 7. Further, as resin layer 53 has been formed by filling the spacing with resin leaving no space, the strain attributable to the thermal stress cannot be relaxed. Therefore, a crack 57 leading to rupture may be created due to the accumulated strain at the root of bump 52.
In the case of the invention disclosed in Japanese Patent Laying-Open No. 8-102466, cover coat (resin) film 66 has been applied to the entire surface of the semiconductor chip, hindering the strain from escaping. The strain is thus accumulated in bump 68 in its root portion, which may result in breakage ultimately.
In the invention disclosed in Japanese Patent No. 2924923, the entire surface of sheet insert 74, except for the hole 76, is closely attached to the surface of the chip. Thus, stress occurs at the interface of sheet insert 74 itself and chip 70 due to the difference of their thermal expansion, which may cause detachment thereof. Such detachment of different materials within the semiconductor device structure allows penetration of water, which would then possibly cause electrical short to circuits on the chip, failure such as package crack due to an increased volume under high temperature, or other problems. Further, sheet insert 74 itself may swell with ambient moisture or expand by heat, of which effects on reliability are innegligible.
In addition, a problem common to these conventional techniques is that they have been manufactured with a large number of steps including sputtering and photolithography employing high-cost processing. This increases the manufacturing cost of the semiconductor device itself, which again suppresses the spread of such device.
An object of the present invention is to provide a semiconductor device having a structure permitting relaxation of stress produced after mounting.
Another object of the present invention is to provide a method of manufacturing a semiconductor device having a structure permitting relaxation of stress produced after mounting.
According to an aspect of the present invention, the semiconductor device having a plurality of externally connecting electrodes arranged on a semiconductor chip includes: on-chip electrodes; resin members formed separately from each other and provided corresponding to the plurality of externally connection electrodes; and interconnections connecting the corresponding on-chip electrode and the corresponding externally connecting electrode.
The resin members provided corresponding to the plurality of externally connecting electrodes are formed separately from each other. Therefore, it is possible to effectively relax thermal stress created at the externally connecting electrodes.
According to another aspect of the present invention, the semiconductor device having a plurality of externally connecting electrodes arranged on a semiconductor chip includes: on-chip electrodes; resin members in a tapering form provided corresponding to the plurality of externally connecting electrodes; and interconnections formed along a slope of the resin member to connect the corresponding on-chip electrode and the corresponding externally connecting electrode.
As the interconnection is formed along the slope of the resin member, the manufacture is simple, and thus, productivity is improved.
According to a further aspect of the present invention, the semiconductor device having a plurality of externally connecting electrodes arranged on a semiconductor chip includes: on-chip electrodes; a resin layer formed to cover the semiconductor chip, having at least one aperture, the externally connecting electrodes being to be formed directly above the resin layer; and interconnections connecting the corresponding on-chip electrode and the corresponding externally connecting electrode.
As the externally connecting electrodes are formed directly above the resin layer, and as at least one aperture is formed in the resin layer, it is possible to effectively relax the thermal stress produced at the externally connecting electrodes.
According to a still further aspect of the present invention, the method of manufacturing a semiconductor device having a plurality of externally connecting electrodes arranged on the semiconductor chip includes the steps of: providing an insulating film on the semiconductor chip at least in a region except on-chip electrode portions; forming resin members or a resin layer at positions where the plurality of externally connecting electrodes are to be formed; forming interconnections connecting the corresponding on-chip electrode and the corresponding externally connecting electrode; providing a material for protection of at least the interconnections; and forming the externally connecting electrodes on the resin members or the resin layer.
As the externally connecting electrodes are formed on the resin members or the resin layer, it is possible to manufacture a semiconductor device permitting relaxation of thermal stress.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.